Invalidation of instruction cache line during reset handling

Details Invalidation of instruction cache line during reset handling Invalidation of instruction cache line during reset handling

2007-04-10

2007-04-10

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000

Reexamination Certificate

active

10815559

ABSTRACT:
Methods and apparatus are provided for handling events such as faults and resets. Specialized circuitry or hardware is provided within a processor to invalidate the cache line associated with the processor cache reset address. Based on the invalided state of the cache reset address line, the processor obtains new instructions from data memory. The new instructions can be configured to invalidate the remaining cache lines using software mechanisms.

REFERENCES:
patent: 5699551 (1997-12-01), Taylor et al.
patent: 5784625 (1998-07-01), Walker
patent: 6681296 (2004-01-01), Liao et al.
patent: 6859862 (2005-02-01), Liao et al.
patent: 6978357 (2005-12-01), Hacking et al.
patent: 2002/0062424 (2002-05-01), Liao et al.
Bernd Paysan, “A Four Stack Processor”, http://www.jwdt.com/˜paysan/4stack.pdf, Apr. 25, 2000, 25 pages.

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