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Wait-free parallel data cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Warm start cache recovery in a dual active controller with...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Way prediction logic for cache array

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Way prediction logic for cache array

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Way prediction structure for predicting the way of a cache in wh

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Way prediction unit and a method for operating the same

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Way-predicting cache memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Web cache memory device and browser apparatus utilizing the...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Web cache performance by applying different replacement...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Web object caching and apparatus for performing the same

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Wide-port context cache apparatus, systems, and methods

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Wide-port context cache apparatus, systems, and methods

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Word selection logic to implement an 80 or 96-bit cache SRAM

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Word selection logic to implement an 80 or 96-bit cache SRAM

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Word selection logic to implement an 80 or 96-bit cache SRAM

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Worm magnetic storage device

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Write back and invalidate mechanism for multiple cache lines

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Write back cache memory control within data processing system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Write barrier for data storage integrity

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Write cache for servicing write requests within a predetermined

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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