Interconnect transaction translation technique

Details Interconnect transaction translation technique Interconnect transaction translation technique

2005-08-08

2009-06-09

Song, Jasmine (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S146000

Reexamination Certificate

active

07546421

ABSTRACT:
A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined for a processor core within a multi-core processor into a fewer number of operations to be delivered to the processor core and translates a response from the core into two or more system response operations corresponding to the two or more system operations.

REFERENCES:
patent: 5926832 (1999-07-01), Wing et al.
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6604185 (2003-08-01), Fromm
patent: 2007/0055827 (2007-03-01), Tsien

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