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First-in, first-out memory system with reduced cycle latency

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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First-in-first-out memory system and method for providing same

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flash memory incorporating microcomputer having on-board writing

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flash ROM sharing between a processor and a controller

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flash translation layer cleanup system and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flexible cache-coherency mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flexible cache-coherency mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flexible mechanism for enforcing coherency among caching...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flexible mounting and unmounting of user removable media

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flexible non-volatile memory controller with boot block emulatio

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flushing cached data upon power interruption

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Flushing of cache memory in a computer system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Folding for a multi-threaded network processor

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Forced transaction log posting using a least busy storage media

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Forward progress on retried snoop hits by altering the coherency

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Forward state for use in cache coherency in a multiprocessor...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Fractional caching

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Free memory manager scheme and cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Free memory manager scheme and cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Front end system having multiple decoding modes

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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