Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-10-27
1999-02-02
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711103, 711202, G06F 1216
Patent
active
058676414
ABSTRACT:
A system and method of cleaning up a full erase unit in a flash translation layer, including moving all valid blocks on the full erase unit to a corresponding address location on a predetermined transfer unit, and then erasing the contents of the full erase unit. After erasure, the formerly full erase unit is redesignated to become the next transfer unit to which the contents of the next full unit will be transferred. The method also includes determining whether a criterion has been met for cleanup to be undertaken. The criteria for undertaking cleanup includes determining whether the number of free blocks is greater than a threshold which is a function of twice the number of bad blocks in the transfer erase unit plus twice the number of flash translation layer structure blocks in the full erase unit.
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Nguyen Hiep T.
Sabath Robert P.
SCM Microsystems (U.S.) Inc.
Swann Tod R.
Weller Edward B.
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