Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-02-17
2000-10-24
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711141, 711144, 711145, G06F 1300
Patent
active
061382183
ABSTRACT:
When a device snooping the system bus of a multiprocessor system detects an operation requesting data which is resident within a local memory in a coherency state requiring the data to be sourced from the device, the device attempts a intervention. If the intervention is impeded by a second device asserting a retry, the device sets a flag to provide historical information regarding the failed intervention. On a subsequent snoop hit to the same cache location, if the device again asserts an intervention and the snooped operation is again retried, the device undertakes an action to alter the coherency state of the requested cache item towards an ultimate coherency state expected to be the result of the original operation requesting the cache item. In the case where the requested cache item includes modified data resident in the device's local memory, the action may include a push operation writing the requested cache item to system memory. This operation may be snooped by other devices from the system bus to update their local memories. In the case where the requested cache item includes data in a coherency state other than the modified state, the action may include simply altering the coherency state to a shared or invalid state.
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Arimilli Ravi Kumar
Dodson John Steven
Lewis Jerry Don
Cabeca John W.
Emile Volel
International Business Machines - Corporation
Tzeng Fred F.
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