Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-03-30
2004-03-23
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S207000, C711S145000, C713S001000
Reexamination Certificate
active
06711653
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to computer systems and, in particular, to mechanisms for maintaining cache coherency in computer systems
2. Background Art
A computer system typically includes a processor core to execute instructions on operands and a memory system to provide the operands and instructions (“data”) to the processor core. The memory system is organized as a hierarchy that includes one or more caches, a random access memory, and a mass storage medium such as a hard disc. Data is distributed among the various storage structures in a manner designed to provide fast access to the data which is most frequently used. This distribution is governed, in part, by the cache management policy implemented by the computer system.
Programs executed by the processor core use logical addresses to refer to the data they manipulate. Logical addresses are independent of the actual location of stored data in the memory system, which allows these programs to run without the need for detailed information about the computer system. The actual storage locations in the memory system are indicated by physical addresses. The operating system that runs on the computer system determines the mapping between logical addresses and the physical addresses. Operating systems typically maintain a page table in main memory to store logical-to-physical address translations.
A processor that had to access the page table for each memory reference would be unnecessarily slow, since main memory accesses have relatively long latencies. Most memory systems include a translation look-aside buffer (TLB) to store near the processor core the physical address translations for recently referenced logical addresses. The TLB may also store memory attributes, which define, for example, the speculative, cacheability, and write-policies of the physical address locations referenced through the logical address. The memory attributes may be used by the computer system to manage the distribution of data among the caches and memory, order memory accesses, and ensure coherency among the different portions of the memory system. For one common TLB configuration, a portion of a logical address forms an address tag of a TLB entry. The physical address to which the logical address maps is stored in one data field of the entry and the memory attribute of the physical address is stored in another data field of the entry.
A complicating feature associated with address translation is that the operating system may map more than one logical address to the same physical address. In doing so, the operating system may associate a different memory attribute with each logical address that maps to the physical address. For example, the attribute associated with one logical address may indicate that the referenced data is cacheable, while the attribute associated with the other logical address may indicate that referenced data is uncacheable. Because the attributes are used to manage the caching strategy employed for different data blocks, a discrepancy in memory attributes can create incoherence between the cache and main memory data if no mechanism is provided to identify and handle the conflict.
Memory attribute aliasing (MAA) occurs when a memory page is accessed with inconsistent memory attributes. For example, a first reference to a memory address may indicate a write-back (WB) memory attribute, which identifies the targeted data as suitable for caching. A subsequent reference may indicate an uncacheable (UC) memory attribute for the same memory address (or an overlapping memory address). The cached data will be missed by the subsequent access because caches are not ordinarily searched for UC memory references. System environments that support MAA provide mechanisms to identify these inconsistencies and ensure coherency between the different storage structures of the memory system. For example, computer systems based on the x86 architecture of Intel® Corporation of Santa Clara, Calif., support MAA. This support requires additional hardware and typically carries a performance hit because additional steps are required to identify and manage memory attribute conflicts.
Some programming environments avoid the performance hit associated with MAA by allowing no more than one reference to a physical memory location to reside in the cache subsystem at a given time. For example, computer systems based on IA64, UNIX or LINUX programming environments obtain higher performance by relying on their operating systems to prevent MAA (IA64 is the 64-bit programming environment developed by Intel® Corporation). However, if these environments are implemented on processors that support MAA, they will lose this performance benefit.
The present invention addresses these and other issues related to supporting MAA.
REFERENCES:
patent: 5544345 (1996-08-01), Carpenter et al.
patent: 5781774 (1998-07-01), Krick
Motorola, MC88110 Second Generation RISC Microprocessor User's Manual, ©1991, p. 6-5-6-12.
Hammond Gary N.
Quach Nhon
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen T
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