First-in, first-out memory system with reduced cycle latency

Details First-in, first-out memory system with reduced cycle latency First-in, first-out memory system with reduced cycle latency

2007-08-07

2007-08-07

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S105000, C710S052000, C710S056000, C710S057000

Reexamination Certificate

active

10839402

ABSTRACT:
A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

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