Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-07-26
2005-07-26
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S142000, C711S143000, C711S144000, C711S146000
Reexamination Certificate
active
06922756
ABSTRACT:
Described herein is a cache coherency protocol having five states: Modified, Exclusive, Shared, Invalid and Forward (MESIF). The MESIF cache coherency protocol includes a Forward (F) state that designates a single copy of data from which further copies can be made. A cache line in the F state is used to respond to request for a copy of the cache line. In one embodiment, the newly created copy is placed in the F state and the cache line previously in the F state is put in the Shared (S) state, or the Invalid (I) state. Thus, if the cache line is shared, one shared copy is in the F state and the remaining copies of the cache line are in the S state.
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Goodman James R.
Hum Herbert H. J.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen T
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