Miss-under-miss processing and cache flushing

MMU descriptor having big/little endian bit to control the...

Mobile client computer system with flash memory management utili

Modified Harvard architecture processor having program...

Modified indirect addressing for file system

Multi-hit control method for shared TLB in a multiprocessor...

Multi-level page cache for enhanced file system performance...

Multi-processor system which provides for translation look-aside

Multi-set block erase

Multi-tiered memory bank having different data buffer sizes...

Multidimensional network sorter integrated circuit

Multifunctional access devices, systems and methods

Multilevel semiconductor memory, write/read method...

Multiple address translations

Multiple page size address translation incorporating page...

Multiple page size address translation incorporating page...

Multiple patches to on-chip ROM in a processor with a...

Multiplexing DRAM control signals and chip select on a processor

Multiprocessor cache coherence management

Multiprocessor system having a shared main memory accessible...