Multiple page size address translation incorporating page...

Details Multiple page size address translation incorporating page... Multiple page size address translation incorporating page...

2007-10-16

2007-10-16

Bertram, Ryan (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S202000, C711S204000, C711S205000

Reexamination Certificate

active

11035556

ABSTRACT:
Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.

REFERENCES:
patent: 6205531 (2001-03-01), Hussain
patent: 6625715 (2003-09-01), Mathews
patent: 2005/0071601 (2005-03-01), Luick
“Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB”, Andre Seznec, IEEE Transactions on Computers, Oct. 9, 2003.
IBM Patent Application, U.S. Appl. No. 10/730,953, by Jason N. Dale, et al., filed Dec. 9, 2003, “A Method of Efficiently Handling Multiple Page Sizes in an Effective to Real Address Translation (ERAT) Table”.

Affiliated with

Also associated with

Rating

Multiple page size address translation incorporating page... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple page size address translation incorporating page..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple page size address translation incorporating page... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3824876