Multiple patches to on-chip ROM in a processor with a...

Details Multiple patches to on-chip ROM in a processor with a... Multiple patches to on-chip ROM in a processor with a...

2007-09-11

2007-09-11

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S102000, C711S118000, C711S122000, C717S168000

Reexamination Certificate

active

10754252

ABSTRACT:
A programmable address decoder is common to the on-chip ROM and on-chip RAM. The programmable address decoder conditionally routes accesses to portions of the ROM to the RAM. The ROM address space is mapped to RAM via a set of configuration registers. This permits patched ROM program code and data table to be stored in on-chip RAM. The patched code and configuration data is stored in an off-chip non-volatile memory. This patch code and the configuration to use is loaded into the RAM and configuration registers on system bootstrap procedure.

REFERENCES:
patent: 5829012 (1998-10-01), Marlan et al.
patent: 6128751 (2000-10-01), Yamamoto et al.
Handy, Jim. “The Cache Memory Book, Second Edition”, Academic Press, Inc. © 1998, pp. 12 & 89-97.

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