Miss-under-miss processing and cache flushing

Details Miss-under-miss processing and cache flushing Miss-under-miss processing and cache flushing

2007-08-16

2011-10-11

Krofcheck, Michael (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S118000, C711S122000, C711S202000, C711SE12057, C711SE12061

Reexamination Certificate

active

08037281

ABSTRACT:
Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.

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