Multiple page size address translation incorporating page...

Details Multiple page size address translation incorporating page... Multiple page size address translation incorporating page...

2007-04-10

2010-06-15

Chace, Christian P (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S169000, C711S202000, C711S207000

Reexamination Certificate

active

07739477

ABSTRACT:
Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.

REFERENCES:
patent: 6205531 (2001-03-01), Hussain
patent: 6625715 (2003-09-01), Mathews
patent: 7159095 (2007-01-01), Dale et al.
patent: 2002/0133685 (2002-09-01), Kalyanasundharam
patent: 2003/0177335 (2003-09-01), Luick
patent: 2005/0027961 (2005-02-01), Zhang
patent: 2005/0071601 (2005-03-01), Luick
“Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB”, Andre Seznec, IEEE Transaction on Computers, Oct. 9, 2003.

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