Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-11-08
2005-11-08
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S201000, C711S202000, C711S203000, C711S205000, C711S206000, C711S207000, C711S211000, C714S024000, C714S029000, C714S030000, C714S035000, C714S047300, C714S729000, C714S730000
Reexamination Certificate
active
06963963
ABSTRACT:
A data processing (10) includes memory management circuitry (14) which allows additional control over the physical address (83) and over the address attributes (84) which are provided for use by data processing system (10). One use of this additional control over the physical address (83) and over the address attributes (84) is to avoid address translation failure and unintended modification of cache (13) and memory (18) system state during debugging.
REFERENCES:
patent: 4888688 (1989-12-01), Hartvigsen
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5682310 (1997-10-01), Pedneau
patent: 5900014 (1999-05-01), Bennett
patent: 6446221 (2002-09-01), Jaggar et al.
patent: 6499123 (2002-12-01), McFarland et al.
patent: 6748558 (2004-06-01), Gonzales et al.
patent: 2004/0019827 (2004-01-01), Rohfleisch et al.
MacNamee et al., Dec., 2000, Computing & Control Engineering Journal, vol. 11, pp. 295-303.
“PCI Arbiter Core,” Actel Corporation, Jan. 2002, pp. 1-3.
Section 3, Memory Management Unit (MC68040 and MC68LC040); MC68040, MC68EC040, MC68LC040 Microprocessors User's Manual, Third Edition, Motorola, 1992, pp. 3-1 to 3-34.
Section 5, Signal Description; MC68040, MC68EC040, MC68LC040 Microprocessor User's Manual, Third Edition, Motorola, 1992, pp. 5-1 to 5-17.
Section 5, Signal Description, Enhanced 32-Bit, MC68030 Microprocessor User's Manual, Third Edition, Motorola, 1990, pp. 5-1 to 5-12.
Section 9, Memory Management Unit, Enhanced 32-Bit, MC68030 Microprocessor User's Manual, Third Edition, Motorola, 1990, pp. 9-1 to 9-86.
Section 12, Applications Information, Enhanced 32-Bit, MC68030 Microprocessor User's Manual, Third Edition, Motorola, 1990, pp. 12-1 to 12-46.
Chiu Joanna G.
Farrokh Hashem
Freescale Semiconductor Inc.
Hill Susan C.
Sparks Donald
LandOfFree
Multiprocessor system having a shared main memory accessible... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiprocessor system having a shared main memory accessible..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor system having a shared main memory accessible... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3498853