Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-06-01
2004-04-27
Robertson, David L. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
06728856
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a modified Harvard architecture processor having data memory space mapped to program memory space.
BACKGROUND OF THE INVENTION
Processors, including microprocessors, digital signal processors and microcontrollers, operate by running software programs that are embodied in one or more series of program instructions stored in a memory. The processors run the software by fetching the program instructions from the series of program instructions, decoding the program instructions and executing them. In addition to program instructions, data is also stored in memory that is accessible by the processor. Generally, the program instructions process data by accessing data in memory, modifying the data and storing the modified data into memory.
One well-known architecture for processors is known as the Harvard architecture. In this architecture, data and program instructions are stored in separate memories that can be accessed simultaneously. Because of this simultaneous access, the Harvard architecture provides significant processing speed advantages over other architectures. A typical Harvard architecture processor that includes internal memory includes two separate memories, one for data, and one for program instructions. In order to expand the memory capacity of such a processor, memory external to the processor must be added. However, since a Harvard architecture processor has two separate memories, in order to expand both data memory and program instruction memory, two separate external memories must be added. This is a significant disadvantage when low-cost systems are being built. Some conventional processors provide the capability to access data that is stored in program instruction memory using special instructions, but this is a limited solution.
A need arises for a processor having an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory.
SUMMARY OF THE INVENTION
The present invention is a processor that has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows data that is stored in the program memory space to be accessed as though it were actually stored in data memory space, using standard data memory access instructions, including arithmetic and logical operation instructions. The processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories, or two external memory busses, in order to expand both data memory and program instruction memory. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data and without using special purpose instructions.
According to the present invention, a processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space.
In one aspect of the present invention, the processor may be operably connected to an external memory device operable to store program instructions and data. The processor may further comprise circuitry operable to map at least a portion of the external memory device to the data memory space. The external memory device may further comprise program memory space. The portion of the external memory device that is mapped to the data memory space may be separate from the program memory space in the external memory device or the portion of the external memory device that is mapped to the data memory space may overlap with the program memory space in the external memory device.
In one aspect of the present invention, at least a portion of the program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space. The processor may be operably connected to an external memory device operable to store program instructions and data. At least a portion of the external memory device may be mapped to the program memory space that is mapped to the data memory space.
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pate
Catherwood Michael
Conner Joshua M.
Grosbach James H.
Microchip Technology Incorporated
Robertson David L.
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