Multi-processor system which provides for translation look-aside

Details Multi-processor system which provides for translation look-aside Multi-processor system which provides for translation look-aside

1996-07-11

1999-08-31

Lane, Jack A.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

G06F 1210

Patent

active

059467177

ABSTRACT:
In a multi-processor system, a translation look-aside buffer in a processor can be invalidated without stopping operations of other processors of the multi-processor system. Each processor has a range comparator including an address compare circuit which detects whether a logical address to access the main storage is in an address range being invalidated (e.g., updated), a pending indicator which stops translating the logical address when the address is detected to be in the address range, and a restart indicator which restarts translation of the logical address when the logical address is out of the address range.

REFERENCES:
patent: 4733350 (1988-03-01), Tone et al.
patent: 5437017 (1995-07-01), Moore et al.
patent: 5440710 (1995-08-01), Richter et al.
patent: 5455922 (1995-10-01), Eberhard et al.
patent: 5497480 (1996-03-01), Hayes et al.
patent: 5710903 (1998-01-01), Horiuchi et al.
French Search Report dated Aug. 29, 1997 (with English translation of pertinent portion indicating degree of relevance).

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