Multi-set block erase

Details Multi-set block erase Multi-set block erase

2000-11-28

2003-09-16

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S005000, C711S103000, C365S230030

Reexamination Certificate

active

06622230

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of flash memory devices. More particularly, the invention relates to both a mechanism and method for multi-set block erase in NAND-based flash memory devices.
BACKGROUND OF THE INVENTION
The overall array architecture for memory section of a typical NAND-based flash memory device comprises a core memory accessed by an upper and lower bank of page buffers and a right and left bank of word line or X-decoders. The core memory contains information stored in blocks of memory and individual memory cells or elements within the memory blocks. The right and left word line or X-decoders are used to access specific memory cells within each memory block and the upper and lower bank of page buffers provide the input and output circuitry for each memory cell. The X-decoders contain numerous final decoder circuits, each with a high voltage generating pump. There is generally one final decoder circuit for each memory block. Each final decoder circuit is linked by various predecoder output lines to a predecoder circuit.
The architecture of one memory block in the typical NAND-based flash memory device comprises the individual memory elements and select gates. The memory elements and select gates are embodied in non-volatile, floating gate transistors that may be programmed to a logic state of 0, 1, or other states depending on the particular type of transistor and programming used. The control gates of the transistors that comprise the individual memory elements and select gates in each memory block are addressed by word lines controlled by the addressing system. The memory elements are connected in series with each other and the select gates. The select gates, at the ends of the chain of memory cells, are connected with either the array common voltage Vss or a bitline. A page buffer is connected with a memory block via a bitline. The page buffer includes transistors and supporting circuitry that regulate the flow of data into and out of the memory block and into and out of the external system.
The array architecture associated with the memory device is shown in FIG.
1
. The array contains N individual page buffers
110
in each bank of page buffers
102
,
104
; thus, as there are both an upper
102
and lower
104
bank of page buffers, one entire page or word line
112
contains 2N bits. Left
106
and right
108
banks of X-decoders are used to select a particular word line. The core memory
100
is split into a set of M memory blocks
114
with each memory block
114
being L pages wide. This results in a 2N bits/page×L pages/memory block×M memory blocks/core memory=2×L×M×N bytes/core memory. One example of an array architecture used is 256 individual page buffers, a set of 1024 memory blocks with each memory block being 16 pages wide. This results in a 2×256 bytes/page×16 pages/memory block×1024 memory blocks/core memory=8M bytes/core memory. Of course, any numbers presented here are merely illustrative of the principle of the invention as a whole. Those ordinarily skilled in the art will appreciate that the numbers associated with any of these elements, as well as the number of memory cells or elements in the overall device, may be changed without departing from the spirit and scope of the invention.
FIG. 2
shows the architecture of one memory block
114
in the NAND-based flash memory device of
FIG. 1
along with the associated page buffer
110
. The memory block
114
comprises many parallel strings like the string of
16
individual memory elements
130
-
145
and two select gates, SG
1
116
and SG
2
118
, for example. As stated before, non-volatile transistors embody the memory elements
130
-
145
and select gates
116
,
118
. The word lines
151
-
166
and select gate lines
150
,
167
are connected with the control gates of the memory elements
130
-
145
and select gates
116
,
118
. The memory elements
130
-
145
and select gates SG
1
116
and SG
2
118
are connected in series. Specifically, the source and drain of the memory elements
130
-
145
are connected to each other in series. Thus, the source of the first memory element
130
is tied to the drain of the memory second element
131
, the source of the second memory element
131
is tied to the drain of the third memory element
132
, etc. Accordingly, the select gates
116
,
118
are connected to the ends of the chain of memory elements
130
-
145
. The source of SG
1
116
is connected with the drain of the first memory element
130
, while the drain of SG
1
116
is connected with a bitline
170
. Similarly, the drain of SG
2
118
is connected with the source of the last memory element
145
and the source of SG
2
118
is connected with the array common (usually ground) voltage Vss
172
.
The memory block
114
is connected with a page buffer
110
via a bitline
170
. The page buffer
110
includes necessary circuitry well known in the art. The necessary circuitry may include, for example, a latch for latching data onto and out of the bitline
170
, input/output circuitry for transferring data to the external system and assorted supporting circuitry inherent in the necessary circuitry.
Individual memory elements can undergo three distinct operations, which are shown in
FIGS. 3
,
4
and
5
. The three operations are Program, shown in
FIG. 3
, Erase, shown in
FIG. 4
, and Read, shown in
FIG. 5
, and are described below. This discussion will be limited to standard, n-channel, NAND-based non-volatile memory elements, although those ordinarily skilled in the art will appreciate that the basic operations described herein can be easily extended to at least NOR-based non-volatile memory elements and multi-level non-volatile memory elements in which more than two states can be programmed.
The structure of the memory element
200
is well known in the art: a p-type semiconductor well
210
is disposed within a n-type semiconductor well
206
. The n-type semiconductor well
206
is contained within a p-type semiconductor substrate
202
. A set of n-type semiconductor junctions comprising the source
204
and drain
208
are disposed within the p-type semiconductor well
210
. The p-type semiconductor well
210
and n-type semiconductor well
206
are usually maintained at the same voltage during device operation to avoid current flow from one of the well regions to the other.
The memory element further includes a control gate
212
and a floating gate
214
. The gates
212
,
214
are conventionally formed from polysilicon deposited and patterned on the surface of the substrate, although the floating gate
214
may alternately be formed from an ONO layer. The gates
212
,
214
are formed such that an oxide is formed on part of the substrate with the floating gate
214
formed above the oxide. The control gate
212
is formed above the floating gate
214
and isolated from the floating gate
214
by a second oxide. Control signals are applied to the control gate
212
.
During the program operation, as shown in
FIG. 3
, both the source
204
and the drain
208
of the memory element
200
are connected with Vss (usually ground). Prior to programming, the threshold voltage (or turn-on voltage) of the MOSFET is generally designed to be a negative voltage, so that a channel
216
of electrons
218
exists in the p-type semiconductor well
210
when the gate
212
is grounded. The channel
216
is disposed between the source
204
and drain
208
of the memory element
200
. A large positive voltage is applied to the control gate
212
, which causes electrons
218
to be trapped onto the floating gate
214
via Fowler-Nordheim tunneling. The threshold voltage of the transistor is increased if electrons are trapped on the floating gate
214
. In this case, the threshold voltage of the programmed memory element changes from a negative voltage to a positive voltage.
During the erase operation, as shown in
FIG. 4
, the source
204
and the drain
208
of the memory element
200
are left floating wh

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