Large memory allocation method and apparatus

Latency tolerant distributed shared memory multiprocessor...

Legacy MIL-STD-1750A software emulator address translation...

Leverage guest logical to physical translation for host-side...

Limited virtual address aliasing and fast context switching with

Linked list DMA descriptor architecture

Linked list memory and method therefor

Load page table entry address instruction execution based on...

Local memory management system with plural processors

Local memory management system with plural processors

Location-independent raid group virtual block management

Location-independent RAID group virtual block management

Location-independent RAID group virtual block management

Logical address structure for disk memories

Logical cache memory storing logical and physical address inform

Logical library architecture for data storage applications...

Logical storage of UDF descriptors by mapping a plurality of...

Logical unit number increasing device, and logical unit...

Logically partitioning different classes of TLB entries...

Lookaside buffer for address translation in a computer system