Multi-hit control method for shared TLB in a multiprocessor...

Details Multi-hit control method for shared TLB in a multiprocessor... Multi-hit control method for shared TLB in a multiprocessor...

2004-11-15

2009-11-10

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S202000, C711S203000, C711S205000, C711S210000

Reexamination Certificate

active

07617379

ABSTRACT:
The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.

REFERENCES:
patent: 5680566 (1997-10-01), Peng et al.
patent: 5893931 (1999-04-01), Peng et al.
patent: 2004/0064654 (2004-04-01), Willis et al.
patent: 0244532 (1987-11-01), None
patent: 2-300951 (1990-12-01), None
patent: 11-501745 (1999-02-01), None

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