Multi-tiered memory bank having different data buffer sizes...

Details Multi-tiered memory bank having different data buffer sizes... Multi-tiered memory bank having different data buffer sizes...

2005-05-24

2005-05-24

Elmore, Stephen (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S118000, C711S120000, C711S168000, C711S170000, C711S209000

Reexamination Certificate

active

06898690

ABSTRACT:
An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.

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