Reducing clock skew in clock gating circuits
Reducing datapath widths by rebalancing data flow topology
Reducing datapath widths responsively to upper bound on...
Reducing design execution run time bit stream size for...
Reducing equivalence checking complexity using inverse function
Reducing I/O supply noise with digital control
Reducing time to design integrated circuits including...
Reducing time to measure constraint parameters of components...
Reducing variation in randomized nanoscale circuit connections
Reducing verification time for integrated circuit design...
Reduction of cross-talk noise in VLSI circuits
Reduction of process antenna effects in integrated circuits
Reduction of storage elements in synthesized synchronous...
Reduction of storage elements in synthesized synchronous...
Redundant via rule check in a multi-wide object class design...
Redundantly tied metal fill for IR-drop and layout density...
Reference image generation from subject image for...
Reformulation of the finite-difference time-domain algorithm...
Region-based voltage drop budgets for low-power design
Regional clock skew measurement technique