Reducing equivalence checking complexity using inverse function

Details Reducing equivalence checking complexity using inverse function Reducing equivalence checking complexity using inverse function

2006-12-05

2006-12-05

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S016000

Reexamination Certificate

active

07146589

ABSTRACT:
One embodiment of the present invention determines equivalence between a first circuit and a second circuit. The first circuit represented by a first circuit function is decomposed into first and second decomposition circuits represented by first and second decomposition functions, respectively. The first circuit has a plurality of first primary inputs and first primary outputs. The plurality of the first primary inputs includes first and second primary input subsets. A reducing function of a reducing circuit is selected for the first decomposition function to reduce complexity of a first composition of the first circuit function and the reducing function. Equivalence is determined between the first composition with a second composition of the reducing function and a second circuit function of a second circuit. The second circuit has a plurality of second primary inputs and second primary outputs matching to the plurality of the first primary inputs and the first primary outputs, respectively.

REFERENCES:
patent: 6086626 (2000-07-01), Jain et al.
patent: 6212669 (2001-04-01), Jain
patent: 6301687 (2001-10-01), Jain et al.
patent: 6334205 (2001-12-01), Iyer et al.
patent: 6530063 (2003-03-01), Andreev et al.
patent: 6560758 (2003-05-01), Jain
patent: 7028278 (2006-04-01), Jain
patent: 2004/0015799 (2004-01-01), Jain
patent: 2006/0129953 (2006-06-01), Jain
Shi-Yu Huang, “Formal Equivalence Checking And Design Debugging”, Kluwer Academic Publishers, 1998, pp. 1-229.
Daniel Brand, “Verification of Large Synthesized Designs”, IEEE, 1993, pg. 534-537.
Wolfgang Kunz, et al., “Recursive Learning: A new Implication Technique for Efficient Solutions to CAD-problems: Test, Verification and Optimization”, IEEE Trans. on Computer-Aided Design, vol. 13, No. 9, Sep. 1994, pp. 1143-1158.
Dhiraj K. Pradhan, et al. Verilat: Verification Using Logic Augmentation and Transformations, IEEE, ICCAD, 1996.

Affiliated with

Also associated with

Rating

Reducing equivalence checking complexity using inverse function does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reducing equivalence checking complexity using inverse function, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing equivalence checking complexity using inverse function will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3713542