Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-03
2007-07-03
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10861812
ABSTRACT:
An integrated circuit and a method for using metal fill geometries to reduce the voltage drop in power meshes. Metal fill geometries are connected to the power mesh using vias or wires at multiple locations. Metal fill geometries are connected to other floating metal fill geometries using vias or wires at multiple locations. The circuit design introduces maximum redundancy between metal fill geometries and power mesh geometries, but partial redundancy between metal fill geometries and metal fill geometries. In particular, the redundancy in connectivity between metal fill geometries and metal fill geometries is kept minimal to reduce the number of geometries introduced. The high redundancy between metal fill geometries and power mesh geometries and the partial redundancy among metal fill geometries result in a smaller IR-drop by reducing the effective resistance on a power mesh. Hence, the invention use redundancy carefully and advantageously to achieve simultaneous metal density and IR-drop optimization without introducing excessive number of metal fill geometries.
REFERENCES:
patent: 5272600 (1993-12-01), Carey
patent: 5602423 (1997-02-01), Jain
patent: 5654216 (1997-08-01), Adrian
patent: 5798937 (1998-08-01), Bracha et al.
patent: 5846854 (1998-12-01), Giraud et al.
patent: 6075711 (2000-06-01), Brown et al.
patent: 6305000 (2001-10-01), Phan et al.
patent: 6748579 (2004-06-01), Dillon et al.
patent: 2001274255 (2001-10-01), None
Ali, I. et al., “Chemical Mechanical Polishing of Interlayer Dieletric: A Review,” Solid State Technology, Oct. 1994, pp. 63-70, vol. 37, No. 10.
Chen, Y. et al., “Area Fill Synthesis for Uniform Layout Density,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Oct. 2002, pp. 1132-1147, Vo. 21, No. 10.
Kouroussis, D. et al., “A Static Pattern-Independent Technique for Power Grid Voltage Integrity Verification,” DAC 2003, Jun. 2-6, 2003, pp. 99-104.
Mitsuhashi, T. et al., “Power and Ground Network Topology Optimization for Cell Based VLSIs,” 29thACM/IEEE Design Automation Conference, 1992, pp. 524-529.
Nanz, G. et al., “Modeling of Chemical-Mechanical Based Polishing: A Review,” IEEE Transactions on Semiconductor Manufacturing, Nov. 1995, pp. 382-389, vol. 8, No. 4.
Qian, H. et al., “Early-Stage Power Grid Analysis for Uncertain Working Modes,” IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, May 2005, pp. 676-682, vol. 24, No. 5.
Singh, J. et al., “Topology Optimization of Structured Power/Ground Networks,” ISPD'04, Apr. 18-21, 2004, pp. 116-123.
“SPIDER: Simultaneous Post-Layout IR-Drop and Metal Density Enhancement with Redundant Fill,” ICCAD '05, Nov. 6-10, 2005, 6 pages.
Stine, B.E. et al., “The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes,” IEEE Transactions on Electron Devices, Mar. 1998, pp. 665-679, vol. 45, No. 3.
Su, H. et al., “Fast Analysis and Optimization of Power/Ground Networks,” IEEE/ACM International Conference on Computer-Aided Design, Nov. 5-9, 2000, pp. 477-480.
Tan, X. D. S. et al., “Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling,” DAC 2001, Jun. 18-22, 2001, pp. 550-554.
Wang, T. et al., “Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm,” 6 Pages. Mar. 2002.
Wu, X. et al., “Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques,” IEEE, 2001, pp. 153-157.
Lin Sun James
Magma Design Automation Inc.
Townsend and Townsend / and Crew LLP
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