Reducing clock skew in clock gating circuits

Details Reducing clock skew in clock gating circuits Reducing clock skew in clock gating circuits

2006-07-25

2006-07-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07082582

ABSTRACT:
One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated clock net that drives a clock input of the sequential element. The sequential element receives a first input net at a data input and generates an output net. The gating circuit has a user-defined clock net. The technique includes determining the gating circuit and transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit.

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