Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-27
2007-03-27
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11163102
ABSTRACT:
The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.
REFERENCES:
patent: 6651198 (2003-11-01), Wang
Goda Ananth Somayaji
Karunanidhi Sugandhini
Puvvada Venugopal
Shah Kalpesh Amrutlal
Tiwari Prapanna
Brady W. James
Do Thuan
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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