Regional clock skew measurement technique

Details Regional clock skew measurement technique Regional clock skew measurement technique

2007-05-08

2007-05-08

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10981958

ABSTRACT:
In an embodiment of the present invention, an integrated circuit (“IC”), such as a field-programmable gate array (“FPGA”) or a complex programmable logic device (“CPLD”), has a global clock buffer coupled to a first regional clock buffer through a first global clock spine. A first flip-flop is close to a first end of a first regional clock spine, and is coupled to a circuit block, such as a configurable logic block. The circuit block is coupled to the global clock buffer through a first routing portion and a second routing portion couples the first flip-flop to the circuit block so as to form a first clock ring allowing measurement of a first clock ring delay. In further embodiments, additional clock rings are configured in the IC, allowing measurements of additional clock ring delays. In suitably symmetric devices, skew along the regional clock spine is calculated from the clock ring delays.

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Xilinx, Inc.; U.S. Appl. No. 10/981,877; filed Nov. 5, 2004; inventors: Bergendahl et al.

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