Reduction of process antenna effects in integrated circuits

Details Reduction of process antenna effects in integrated circuits Reduction of process antenna effects in integrated circuits

1998-12-07

2001-09-18

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S121000, C716S030000

Reexamination Certificate

active

06292927

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to integrated circuits, and more specifically, to reducing process antenna effects in integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are typically fabricated from one or more layers of different materials. Some layers, such as polysilicon layers, are used to form semiconductor devices while other layers, such as patterned metal layers, provide electrical connections between semiconductor devices. Typical integrated circuits include multiple patterned metal layers, with intervening inter-level dielectric layers for electrically insulating the metal layers.
It is well known that certain processes used in semiconductor fabrication, particularly plasma processing, can cause charging of conductor films formed on a wafer surface. For example, polysilicon or metal interconnect structures are known to be particularly susceptible to charge buildup during plasma etching. This phenomenon is sometimes referred to as the “antenna effect” and is believed to be caused by non-uniformities in the plasma across the wafer surface. In some circumstances the charge buildup can damage thin oxides under the interconnect structures, either by shorting or sufficiently weakening the oxides so that they fail during normal device operation. Because of its adverse effects on yield, antenna effects are a critical issue in semiconductor processing.
There are several prior approaches for reducing antenna effects in semiconductor processing. Two prior approaches include changing the processing used to fabricate an integrated circuit and changing the design of an integrated circuit. Examples of changing the processing of an integrated circuit include reducing the excitation frequency, modifying the electrode design of a plasma etcher, eliminating highly electromagnetic gases such as SF
6
from the etch process, modifying the oxide cleaning process and selecting an oxide growth process that yields an oxide that is less susceptible to charging damage. Often several combinations of processing changes are required to provide a significant reduction in antenna effects.
A significant limitation of this approach is that it can be difficult to find a single processing solution that significantly reduces antenna effects under all circumstances because process-induced damage is highly dependent on the particular processing step in which it is implemented. Thus, a processing solution may comprise numerous incremental processing improvements that do not necessarily provide a substantial reduction in antenna effects.
Changing the design of an integrated circuit to reduce antenna effects typically involves changing the layout of an integrated circuit. In the context of integrated circuit design, a “layout” is a set of geometric patterns, typically polygons, that specify the size and location of different types of material used to create semiconductor devices and electrical connections between the devices during fabrication of an integrated circuit. For example, a diffusion window on an integrated circuit may be represented in a layout by one or more polygons which are interpreted by a fabrication facility to mean “diffusion layer geometry.” Other layers of material and features, such as contacts and vias, may also be similarly represented in an integrated circuit layout. The polygons in an integrated circuit layout must meet a set of design rules which define minimum sizes for certain types of material as well as minimum spacing requirements between different types of material. The design rules also specify size and spacing requirements for other layout features such as contacts. In contemporary semiconductor fabrication, integrated circuit layouts are often generated using computer-aided design (CAD) software. Thus, changes to an integrated circuit layout can be made to a data representation of the integrated circuit layout using CAD software.
There are several types of design changes that can be made to reduce antenna effects in an integrated circuit. One type of design change involves providing a discharge path for each device input in the integrated circuit. A discharge path is typically created by connecting a device input through a diode to ground, although other types of discharge paths may be used. Gate array implementations often have unused transistors that can be used for this purpose. As is well known in the art, an unused transistor is easily converted into a diode by connecting the gate to either the drain or source. An interconnect is then added from each device input through an available diode to ground.
The approach of connecting each device input to a discharge path in an integrated circuit layout to reduce antenna effects can have several adverse consequences. First, design costs can increase significantly because every cell in the integrated circuit layout has to be modified and tested. Furthermore, gate arrays do not always have enough unused transistors for the additional discharge paths, requiring that additional devices be added to the integrated circuit layout. These additional devices increase the size of the integrated circuit which is highly undesirable. This problem is even more acute for standard cells that do not ordinarily have any unused transistors. This problem is further exacerbated in custom designs because adding devices can require the entire place and route phase to be repeated. Even if additional devices do not have to be added to the integrated circuit layout, the additional routing attributable to the discharge paths can cause changes to the existing routing, and in some cases increase the size of the layout. Finally, circuit performance can be adversely affected by the additional capacitances attributable to the devices and interconnects.
Another type of design change involves limiting the length of interconnects to keep antenna effects within acceptable limits. As is well known, the amount of charge buildup on a particular interconnect depends on the total area of the particular interconnect. Consequently, during routing, interconnects that exceed acceptable total area limits are segmented and some of the segments moved to a different (higher) metal level. The segments are connected with vias to re-form the interconnects on different levels. However, each segment is short enough to avoid violating the antenna effect limit.
For example, suppose after the place and route phase for an integrated circuit layout that a particular interconnect on metal level three (M
3
) exceeds the acceptable antenna effect limits. The particular interconnect is divided into three segments, two end segments and a middle segment. The middle segment is moved to metal level four (M
4
) while the two end segments remain on M
3
. Two vias are used to connect the middle segment to each of the end segments. The result is an interconnect with three segments where none of the three segments individually violates the antenna effect limit. For longer interconnects, more segments may be required.
Although limiting the length of interconnects can significantly reduce antenna effects in integrated circuits, it is not without its disadvantages. First, this approach can require substantial re-routing of an integrated circuit and in some circumstances the segmentation can cause routing conflicts that ultimately require additional routing to resolve, increase the size of an integrated circuit. For example, in some situations there isn't enough available space in the layout for the new routing. As a result, the routing on other levels may have to be changed to free up space for the new routing. Moreover, the additional vias required to connect the segments can cause the routing to be changed and also increase the size of the integrated circuit because the via landing pads are wider than the interconnects. For example, two parallel interconnects with vias must be spaced farther apart than two similar parallel interconnects without vias. Thus, portions of the integrated circuit may need to be re-routed to accommodate the additional vias. In addition

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