Reducing design execution run time bit stream size for...

Details Reducing design execution run time bit stream size for... Reducing design execution run time bit stream size for...

2007-11-20

2007-11-20

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C714S725000

Reexamination Certificate

active

11064369

ABSTRACT:
A method of testing a programmable logic device (PLD) can include distinguishing between stages within the design that uniquely test a routing resource and stages that do not. The method also can include un-routing at least a portion of the design corresponding to one or more of the stages that do not uniquely test a routing resource. The stage(s) can be excluded from the design. The portion of the design that was un-routed can be re-routed by passing those stages that do not uniquely test a routing resource.

REFERENCES:
patent: 6347378 (2002-02-01), MacArthur et al.
patent: 6581200 (2003-06-01), Chopra et al.
patent: 2005/0108665 (2005-05-01), Neves et al.
U.S. Appl. No. 10/696,357, filed Oct. 28, 2003, Young et al.
U.S. Appl. No. 10/716,947, filed Nov. 18, 2003, Young et al.
U.S. Appl. No. 10/966,643, filed Oct. 15, 2004, Young et al.

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