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Method, recording medium, and design support system for...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Methods and apparatus for layout of multi-layer circuit...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Methods and systems for FPGA rewiring

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Methods and systems for reducing clock skew in a gated clock...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Methods for designing semiconductor device with dynamic...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Methods for forming area-efficient scan chains in integrated...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Methods for hierarchical noise analysis

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Methods of implementing and modeling interconnect lines at...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Modifying integrated circuit layout

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Node spreading via artificial density enhancement to reduce...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Operation timing verifying apparatus and program

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Optimization method for fractional-N phased-lock-loop (PLL)...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Optimization method of integrated circuit design for...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Optimization of ROM structure by splitting

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Optimizing systems-on-a-chip using the dynamic critical path

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Overlay measurement on double patterning substrate

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Parallel intrusion search in hierarchical VLSI designs with...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Pipeline architecture for maximum a posteriori (MAP) decoders

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Place-and-route layout method with same footprint cells

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Placement and routing using inhibited overlap of expanded areas

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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