Method, recording medium, and design support system for...
Methods and apparatus for layout of multi-layer circuit...
Methods and systems for FPGA rewiring
Methods and systems for reducing clock skew in a gated clock...
Methods for designing semiconductor device with dynamic...
Methods for forming area-efficient scan chains in integrated...
Methods for hierarchical noise analysis
Methods of implementing and modeling interconnect lines at...
Modifying integrated circuit layout
Node spreading via artificial density enhancement to reduce...
Operation timing verifying apparatus and program
Optimization method for fractional-N phased-lock-loop (PLL)...
Optimization method of integrated circuit design for...
Optimization of ROM structure by splitting
Optimizing systems-on-a-chip using the dynamic critical path
Overlay measurement on double patterning substrate
Parallel intrusion search in hierarchical VLSI designs with...
Pipeline architecture for maximum a posteriori (MAP) decoders
Place-and-route layout method with same footprint cells
Placement and routing using inhibited overlap of expanded areas