Methods and systems for reducing clock skew in a gated clock...

Details Methods and systems for reducing clock skew in a gated clock... Methods and systems for reducing clock skew in a gated clock...

2009-03-04

2011-12-27

Levin, Naum (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S113000, C716S108000

Reexamination Certificate

active

08086982

ABSTRACT:
Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.

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