Operation timing verifying apparatus and program

Details Operation timing verifying apparatus and program Operation timing verifying apparatus and program

2011-07-05

2011-07-05

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S119000, C703S016000

Reexamination Certificate

active

07975249

ABSTRACT:
An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation timing verifying apparatus and program sets an unreal corner condition that all delay elements present a maximum delay as an operating condition, performs operation timing analysis in the operating condition, thereby extracting an operation-violating circuit path, if any, from a circuit layout, sets a real corner condition that at least one element type of delay elements from among the delay elements present a maximum delay as the operating condition and performs the operation timing analysis on only the operation-violating circuit path to determine again whether an operation violation exists therein.

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Bozorgzadeh et al., “Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 7, Jul. 2004, pp. 1184-1199.

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