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Operation timing verifying apparatus and program

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate

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Optimization method for fractional-N phased-lock-loop (PLL)...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Optimization method of integrated circuit design for...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Optimization of ROM structure by splitting

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Optimizing systems-on-a-chip using the dynamic critical path

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Overlay measurement on double patterning substrate

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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