Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-04-12
2011-04-12
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S116000, C716S136000, C703S016000, C713S002000, C713S100000, C327S157000, C327S147000
Reexamination Certificate
active
07926015
ABSTRACT:
In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented.
REFERENCES:
patent: 3739270 (1973-06-01), Miller et al.
patent: 4363138 (1982-12-01), Franklin et al.
patent: 5909661 (1999-06-01), Ambramovitch et al.
patent: 5991308 (1999-11-01), Fuhrmann et al.
patent: 6327542 (2001-12-01), McBride
patent: 6904110 (2005-06-01), Trans et al.
patent: 6915503 (2005-07-01), Lesea
patent: 7120412 (2006-10-01), Anand
patent: 7181711 (2007-02-01), Foreman et al.
patent: 7183860 (2007-02-01), Staszewski et al.
patent: 7288998 (2007-10-01), Thomsen et al.
patent: 7292947 (2007-11-01), Tabatabaei
patent: 7295077 (2007-11-01), Thomsen et al.
patent: 7310593 (2007-12-01), Hammerschmidt
patent: 7313176 (2007-12-01), Groen
patent: 7321847 (2008-01-01), Welkie et al.
patent: 7365580 (2008-04-01), Martin et al.
patent: 7472362 (2008-12-01), Feng
patent: 7750697 (2010-07-01), Feng
patent: 2003/0224747 (2003-12-01), Anand
patent: 2005/0107970 (2005-05-01), Franch et al.
patent: 2005/0111536 (2005-05-01), Cranford et al.
patent: 2005/0186920 (2005-08-01), Staszewski et al.
patent: 2005/0186933 (2005-08-01), Trans
patent: 2005/0246142 (2005-11-01), Hammerschmidt
patent: 2006/0033582 (2006-02-01), Staszewski et al.
patent: 2006/0202714 (2006-09-01), Hoang et al.
patent: 2006/0245531 (2006-11-01), Leonowich et al.
patent: 2006/0248485 (2006-11-01), Foreman et al.
patent: 2007/0100596 (2007-05-01), Hollis
patent: 2007/0103240 (2007-05-01), Staszewski et al.
patent: 2007/0205833 (2007-09-01), Mar et al.
patent: 2007/0233444 (2007-10-01), O'Mahony et al.
patent: 2009/0015304 (2009-01-01), Yin et al.
patent: 2009/0243674 (2009-10-01), Feng
patent: 2009/0243676 (2009-10-01), Feng
patent: 2010/0249633 (2010-09-01), Droitcour et al.
patent: 2010/0283654 (2010-11-01), Waheed et al.
Notice of Allowance from U.S. Appl. No. 12/060,162 mailed on Jul. 10, 2008.
Final Office Action Summary from U.S. Appl. No. 12/176,500 mailed on Dec. 7, 2009.
Kim, “A Fractional-N-PLL Frequency Synthesizer Design” 2005 IEEE , 2005, pp. 84-87.
Wang, “A Generic Multi-Modulus Divider Architecture for Fractional-N Frequency Synthesisers” 2007 IEEE , 2007, pp. 261-265.
Office Action Summary from U.S. Appl. No, 12/176,500 mailed on Sep. 17, 2009.
International Business Machines - Corporation
Kik Phallaka
Zilka-Kotab, PC
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