Methods and systems for FPGA rewiring

Details Methods and systems for FPGA rewiring Methods and systems for FPGA rewiring

2009-05-26

2011-10-18

Doan, Nghia (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S104000, C716S111000, C716S119000

Reexamination Certificate

active

08042083

ABSTRACT:
There are disclosed a method and system for FPGA rewiring of a circuit. The method comprises: mapping the circuit into a first circuit, the first circuit being logically represented with a plurality of Look-Up Tables; rewiring the first circuit to obtain a second circuit, a mapping area of the second circuit being less than that of the first circuit; mapping the second circuit into a third circuit, the third circuit being logically represented with less Look-Up Tables than the first circuit; and routing the third circuit to generate a FPGA architecture file related to the circuit.

REFERENCES:
patent: 2007/0277161 (2007-11-01), Herbordt et al.
patent: 2009/0249276 (2009-10-01), Wu et al.
Chang, et al. “Postlayout Logic Restructuring Using Alternative Wires”,IEEE, vol. 16, No. 6, Jun. 1997, pp. 587-596.
Chen, et al., “DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs”,Proc. Int'l Conf. on Computer-aided Design, 2004, pp. 752-759.
Cong, et al., “A New Enhanced SPFD Rewiring Algorithm”,Proc. IEEE/ACM International Conference on Computer-aided Design '02, San Jose, CA USA, Nov. 2002, pp. 672-678.
Ling, et al., “FPGA Technology Mapping: A Study of Optimality”,42ndACM/IEEE Design Automation Conference, 2005, pp. 427-432.
Manohararajah, et al., “Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping”,IEEE, vol. 25, No. 11, Nov. 2006, pp. 2331-2340.
Marquardt, et al., “Timing-Driven Placement for FPGAs”,Proc. Int'l Symp. on Field Programmable Gate Arrays, Monterey, CA USA, Feb. 2000, pp. 203-213.
Yamashita, et al., “A New Method to Express Functional Permissibilities for LUT based FPGAs and its Applications”,Proc. IEEE/ACM International Conference on Computer-aided Design '96, San Jose, CA USA, Nov. 1996, pp. 254-261.
Betz et al, “VPR: A New Packing, Placement and Routing Tool for FPGA Research”, 1997 International Workshop on Field Programmable Logic and Applications.
C. W. Chang and M. Marek-Sadowska, “Single-Pass Redundancy Addition and Removal,” inProc. IEEE/ACM International Conference on Computer-aided Design'01, San Jose, CA, USA, Nov. 2001, pp. 606-609.
C. W. Chang and M. Marek-Sadowska, “Who are the Alternative Wires in Your Neighborhood?” inProc. ACM Greak Lakes Symposium on VLSI'01, West Lafayette, USA, Mar. 2001, pp. 103-108.
S. C. Chang, L. P. v. Ginneken, and M. Marek- Sadowska, “Fast Boolean Optimization by Rewiring,” inProc. IEEE/ACM International Conference on Computer-aided Design'96, San Jose, CA, USA, Nov. 1996, pp. 262-269.
Chang et al., “Circuit Optimization by Rewiring”, IEEE Transactions on Computers, vol. 48, No. 9, Sep. 1999. pp. 962-970.
Chang et al., “Perturb and Simplify: Multilevel Boolean Network Optimizer”, IEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, vol. 15, No. 12, Dec. 1996, pp. 1494-1504.
K. T. Cheng and L. A. Entrena, “Multi-Level Logic Optimization by Redundancy Addition and Removal,” inProc. IEEE European Design Automation Conference'93, Paris, France, Feb. 1993, pp. 373-377.
Wu et al., “Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 3, Jun. 2003, pp. 451-460.
Entrena et al., “Combinational and Sequential Logic Optimization by Redundancy Addition and Removal”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, No. 7, Jul. 1995, pp. 909-916.
Iyer et al., “Fire: A Fault-Independent Combinational Redundancy Identification Algorithm”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, No. 2, Jun. 1996, pp. 295-301.
S. Sinha and R. K. Brayton, “Implementation and use of SPFDs in Optimizing Boolean Networks,” inProc. IEEE/ACM International Conference on Computer-aided Design'98, San Jose, CA, USA, Nov. 1998, pp. 103-110.
Y. L. Wu, W. N. Long, and H. B. Fan, “A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks,” inProc. IEEE International Conference on VLSI Design'00, Calcutta, India, Jan. 2000, pp. 268-273.

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