Methods for forming area-efficient scan chains in integrated...

Details Methods for forming area-efficient scan chains in integrated... Methods for forming area-efficient scan chains in integrated...

2011-06-28

2011-06-28

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C714S726000

Reexamination Certificate

active

07971170

ABSTRACT:
A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.

REFERENCES:
patent: 5828579 (1998-10-01), Beausang
patent: 5949692 (1999-09-01), Beausang et al.
Synopsys, “How to Avoid MUXs in Front of Scan Segments”, https://solvnet.synopsys.com, Synopsys, Inc, 2003.

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