Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-08-23
2011-08-23
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S113000, C716S114000, C716S120000
Reexamination Certificate
active
08006213
ABSTRACT:
A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.
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Berry Christopher J.
Hwang Charlie Chornglii
Lewis David Wade
Neves Jose Luis Pontes Correla
Garbowski Leigh Marie
International Business Machines - Corporation
Kinnaman, Jr. William A.
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