Methods for hierarchical noise analysis

Details Methods for hierarchical noise analysis Methods for hierarchical noise analysis

2011-02-08

2011-02-08

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S103000, C716S104000, C716S105000, C703S014000

Reexamination Certificate

active

07886257

ABSTRACT:
Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic circuit such as a digital CMOS circuit. The method includes identifying a cell and identifying the inputs of the cell. For each of the inputs of the cell, a corresponding first upstream circuit component is identified. The identified component is the first component upstream from the cell's input and is directly connected to the input. A noise analysis for the cell is performed based upon the configuration of the cell in combination with the identified upstream circuit components. The result of the analysis for the combination of the cell and the upstream circuit components can then be stored.

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