Concurrently modeling delays between points in static timing...
Constraint based retiming of synchronous circuits
Constraint management and validation for template-based...
Control signal source replication
Controlling operation of a digital system utilizing register...
Conversion of a high-level graphical circuit design block to...
Cost-benefit optimization for an airgapped integrated circuit
Delay analysis apparatus, delay analysis method and computer...
Design Structure for switching digital circuit clock net...
Design-for-test-aware hierarchical design planning
Design-For-testability planner
Determining a cycle basis of a directed graph
Determining clock skew between nodes of an integrated circuit
Directed design space exploration
Dual path static timing analysis
Dynamic critical path detector for digital logic circuit paths
Efficient exhaustive path-based static timing analysis using...
Enhanced verification through binary decision diagram-based...
Enhancing formal design verification by reusing previous...
Fast reduction of system models