Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2008-05-06
2011-10-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S103000, C716S116000, C716S132000
Reexamination Certificate
active
08037435
ABSTRACT:
The time and computational resources needed to evaluate the potential input parameter settings in a design space is decreased by determining probabilities of improvement for input parameter settings in the design space and eliminating input parameter values that have low probabilities of improvement from the design space prior to compilation. The probability of improvement for input parameter settings is an estimate of the likelihood that the compilation of the user design using the set of input parameter settings will improve the performance of the user design with respect to one or more design goals, such as timing, power, or resource usage. The probability of improvement for input parameter settings can be determined from an analysis of the compilation results of sample designs, from attributes and/or constraints of the user design, and/or from a correlation between the results of optimization algorithms applied to the user design.
REFERENCES:
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 5550839 (1996-08-01), Buch et al.
patent: 6026226 (2000-02-01), Heile et al.
patent: 6080204 (2000-06-01), Mendel
patent: 6308313 (2001-10-01), Lakshminarayana et al.
patent: 6434729 (2002-08-01), Alpert et al.
patent: 6446239 (2002-09-01), Markosian et al.
patent: 6449761 (2002-09-01), Greidinger et al.
patent: 6651235 (2003-11-01), Dai et al.
patent: 6691286 (2004-02-01), McElvain et al.
patent: 6721924 (2004-04-01), Patra et al.
patent: 7134100 (2006-11-01), Ravi et al.
patent: 7181703 (2007-02-01), Borer et al.
patent: 7370295 (2008-05-01), Chesal et al.
patent: 7454324 (2008-11-01), Seawright et al.
patent: 7594208 (2009-09-01), Borer et al.
patent: 2003/0229728 (2003-12-01), Hodges
patent: 2004/0261052 (2004-12-01), Perry et al.
patent: 2006/0229753 (2006-10-01), Seskin et al.
Hutton, “Characterization and Automatic Generation of Benchmark Circuits,” Ph.D. Thesis, University of Toronto, chapters 1-3 (1997).
Karchmer et al. sweeper.tcl version 2.3 beta, Altera Corporation San Jose, CA (2002).
“Introduction to Quartus.RTM. II,” product information Altera Corporation San Jose, CA (2003).
Borer Terry
Chesal Ian
Altera Corporation
Ingerman Jeffrey H.
Ropes & Gray LLP
Siek Vuthe
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