Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-06-21
2011-06-21
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
Reexamination Certificate
active
07966592
ABSTRACT:
A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.
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Brown Jeffrey S.
Byrn Jonathan W.
Turner Mark F.
LSI Corporation
Maiorana PC Christopher P.
Whitmore Stacy A
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