Design-For-testability planner

Details Design-For-testability planner Design-For-testability planner

2011-04-12

2011-04-12

Doan, Nghia M (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S107000, C716S108000, C716S109000, C716S111000, C702S108000, C702S109000, C702S110000, C702S111000, C702S112000, C702S117000, C702S126000, C714S025000, C714S057000, C714S724000, C714S742000, C324S076660, C324S076670, C324S093000, C324S096000

Reexamination Certificate

active

07926012

ABSTRACT:
A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.

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Lehner, Testing Stratergy Planning—A tool to support future CAD Systems, 1991, ACM, p. 343-351.
Parimi, N., Gallagher, P., and Foutz, B. “Planning Design-For-Test Synthesis Using a Unified Framework,” Cadence Technical Conference, 2007, Endicott, NY.

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