Determining clock skew between nodes of an integrated circuit

Details Determining clock skew between nodes of an integrated circuit Determining clock skew between nodes of an integrated circuit

2011-08-16

2011-08-16

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S108000, C716S113000, C716S134000

Reexamination Certificate

active

08001504

ABSTRACT:
A set of respective first delay values for paths from a clock source to nodes of the integrated circuit is generated. Respective second delay values for the paths are generated from the clock source through the clock tree to the nodes. Each first delay value corresponds to one of the second delay values for one of the nodes, and each is greater than the corresponding second delay value. A set of common delay values is generated, with each common delay value being a delay for a shared portion of the paths from the clock source through the clock tree to two of the nodes. The determined clock skew is based on the first delay value for a first node, the second delay value for a second node, and the common delay value for the shared portion of the paths from the clock source to the first and second nodes.

REFERENCES:
patent: 7472365 (2008-12-01), Manaker
patent: 7475297 (2009-01-01), Manaker
patent: 2007/0016884 (2007-01-01), Nishimaru
Xilinx, Inc.; U.S. Appl. No. 10/997,565, by Manaker Jr.; filed on Nov. 24, 2004.
Xilinx, Inc.; U.S. Appl. No. 10/997,621, by Manaker Jr.; filed on Nov. 24, 2004.

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