Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-04-05
2011-04-05
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S100000, C716S101000, C716S102000, C716S103000
Reexamination Certificate
active
07921389
ABSTRACT:
In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.
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Roesner Wolfgang
Williams Derek Edward
Dillon & Yudell LLP
Doan Nghia M
International Business Machines - Corporation
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