Design Structure for switching digital circuit clock net...

Details Design Structure for switching digital circuit clock net... Design Structure for switching digital circuit clock net...

2008-08-15

2011-12-27

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

Reexamination Certificate

active

08086977

ABSTRACT:
A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

REFERENCES:
patent: 4423383 (1983-12-01), Svendsen
patent: 5167031 (1992-11-01), Watanabe
patent: 5734877 (1998-03-01), Ries et al.
patent: 6766460 (2004-07-01), Evoy et al.
patent: 7752480 (2010-07-01), Law et al.
patent: 2005/0034090 (2005-02-01), Sato et al.
Office action for pending U.S. Appl. No. 11/465,639, mailed Jan. 13, 2009, 8 pages.

Affiliated with

Also associated with

Rating

Design Structure for switching digital circuit clock net... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design Structure for switching digital circuit clock net..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design Structure for switching digital circuit clock net... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4268699