Fast reduction of system models

Details Fast reduction of system models Fast reduction of system models

2011-05-24

2011-05-24

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

Reexamination Certificate

active

07949970

ABSTRACT:
Techniques are provided for fast reduction of a system model, such as fast parasitics reduction of an electrical design. Delta loops, which comprise three nodes connected by three edges, may be identified. The netlist can be annotated with the number of delta loops to which an edge belongs and a delta loop identifier. Delta loops that share an edge may be assigned the same identifier. Identifying delta loops may be based on the intersection of binary search trees that are based on the netlist. In one embodiment, a cost of removing a node from the netlist is determined. Based on the annotations to the edges connected to a node under consideration for removal, the total number of delta loops that are shared by pairs of edges is determined. Based, at least in part, on the total number of common delta loops, a cost is determined of removing the node.

REFERENCES:
patent: 6842750 (2005-01-01), Andreev et al.
patent: 2003/0043827 (2003-03-01), Teig et al.
patent: 2003/0065965 (2003-04-01), Korobkov
patent: 2006/0047680 (2006-03-01), Paruthi et al.
patent: 2008/0109774 (2008-05-01), Baumgartner et al.
patent: 2008/0282207 (2008-11-01), Baumgartner et al.
Sheehan et al.; “TICER: Realizable Reduction of Extracted RC Circuits”; 1999; IEEE; pp. 1-4.
Guy E. Blelloch et al., “Fast Set Operations Using Treaps,” 10thAnnual ACM Symposium on Parallel Algorithms and Architectures (SPAA'98), Jun. 28-Jul. 2, 1998, Puerto Vallarta, Mexico, pp. 1-11.
Masud H. Chowdhury et al., “Realizable Reduction ofRLCCircuits Using Node Elimination,” 0-7803-7761-3/03/-IEEE, 2003, pp. III-494-III-497.
Conrado Martinez et al., “Randomized Binary Search Trees,” Journal of the ACM, vol. 45, No. 2, Mar. 1998, pp. 288-323.
Zhanhai Qin et al., “Realizable Parasitic Reduction Using Generalized Y-Δ Transformation,” DAC 2003, Jun. 2-6, 2003, Anaheim, CA, USA, pp. 220-225.
Vasant B. Rao et al., “Aggressive Crunching of Extracted RC Netlists,”TAU'02, Dec. 2-3, 2002, Monterey, CA, USA, pp. 70-77.
Bernard N. Sheehan, “TICER: Realizable Reduction of Extracted RC Circuits,” 0-7803-5832-5/99-IEEE, 1999, pp. 200- 203.
Guy E. Blelloch et al., “Fast Set Operations Using Treaps,” 10thAnnual ACM Symposium on Parallel Algorithms and Architectures (SPAA'98), Jun. 28 —Jul. 2 1998, Puerto Vallarta, Mexico, pp. 1-11.
Masud H. Chowdhury et al., “Realizable Reduction ofRLCCircuits Using Node Elimination,” 0-7803-7761-3/03/-IEEE, 2003, pp. III-494 —III-497.
Conrado Martinez et al., “Randomized Binary Search Trees,” Journal of the ACM, vol. 45, No. 2, Mar. 1998, pp. 288-323.
Zhanhai Qin et al., “Realizable Parasitic Reduction Using Generalized Y-ΔTransformation,” DAC 2003, Jun. 2-6, 2003, Anaheim, CA, USA, pp. 220-225.
Vasant B. Rao et al., “Aggressive Crunching of Extracted RC Netlists,”Tau'02, Dec. 2-3, 2002, Monterey, CA, USA, pp. 70-77.
Raimund Seidel et al., “Randomized Search Trees,” Computer Science Division, University of California Berkeley, Universitat des Saarlandes, Saarbrucken, Germany, 33 pages. 1996.
Bernard N. Sheehan, “TICER: Realizable Reduction of Extracted RC Circuits,” 0-7803-5832-5/99-IEEE, 1999, pp. 200-203.

Affiliated with

Also associated with

Rating

Fast reduction of system models does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fast reduction of system models, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast reduction of system models will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2620551