Delay analysis apparatus, delay analysis method and computer...

Details Delay analysis apparatus, delay analysis method and computer... Delay analysis apparatus, delay analysis method and computer...

2011-01-11

2011-01-11

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S106000

Reexamination Certificate

active

07870533

ABSTRACT:
Within-die delay distributions and die-to-die delay distributions of two arbitrary paths in an analysis target circuit are extracted from a delay distribution library, and an effect index indicative of a relative error of an overall path delay distribution of one path and an overall path delay distribution when the two paths are integrated as one path is calculated based on the within-die delay distributions and the die-to-die delay distributions of the two paths. When the effect index is determined to be equal to or above a threshold, the overall path delay distribution of the two paths integrated as one path is calculated. Hence, a path that affects an analysis result alone is selected to execute a statistical Max operation, thereby increasing a speed of delay analysis processing.

REFERENCES:
patent: 5933433 (1999-08-01), Miyashita
patent: 7681161 (2010-03-01), Homma et al.
patent: 2006/0107244 (2006-05-01), Yonezawa
patent: 2008/0178130 (2008-07-01), He
patent: 2005-100310 (2005-04-01), None
Aseem Agarwal et al., “Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations” Proc. ICCAD 2003, pp. 900-907.

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