Design-for-test-aware hierarchical design planning

Details Design-for-test-aware hierarchical design planning Design-for-test-aware hierarchical design planning

2011-05-03

2011-05-03

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S110000, C716S119000, C716S122000

Reexamination Certificate

active

07937677

ABSTRACT:
Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.

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Cote et al. “LogicVision's Complete RTL-to-GDS2 Flow”, http://www.yieldlearning.com/YLR—technical—papers.php, Feb. 18, 2008, 9 pages.

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