Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-03-15
2011-03-15
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S136000
Reexamination Certificate
active
07908575
ABSTRACT:
A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
REFERENCES:
patent: 6131078 (2000-10-01), Plaisted
patent: 7299432 (2007-11-01), Baumgartner et al.
patent: 7337100 (2008-02-01), Hutton et al.
patent: 7350169 (2008-03-01), Baumgartner et al.
patent: 7383166 (2008-06-01), Ashar et al.
patent: 2003/0208730 (2003-11-01), Singhal et al.
patent: 2006/0129953 (2006-06-01), Jain
patent: 2006/0129958 (2006-06-01), Raymond et al.
patent: 2006/0129959 (2006-06-01), Mang et al.
Bertacco et al., The Disjunctive Decomposition of Logic Functions, International Conference on Computer-Aided Design, 1997, pp. 78-82.
Sistla et al., Symmetry and Reduced Symmetry in Model Checking, International Conference on Computer Aided Verification, 2001, pp. 91-103.
Dinh, Paul, Office Action dated Sep. 13, 2007, U.S. Appl. No. 11/143,330.
Dinh, Paul, Notice of Allowance dated Nov. 5, 2007, U.S. Appl. No. 11/143,330.
Dinh, Paul, Office Action dated Apr. 23, 2009, U.S. Appl. No. 11/969,741.
Dinh, Paul, Office Action dated Apr. 23, 2009, U.S. Appl. No. 11/969,761.
Do, Thuan, Office Action dated Aug. 13, 2010, U.S. Appl. No. 11/952,535.
Baumgartner Jason Raymond
Kanzelman Robert Lowell
Mony Hari
Paruthi Viresh
Dillon & Yudell LLP
Do Thuan
International Business Machines - Corporation
LandOfFree
Enhanced verification through binary decision diagram-based... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhanced verification through binary decision diagram-based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced verification through binary decision diagram-based... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2697165