Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-06-14
2011-06-14
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S113000
Reexamination Certificate
active
07962871
ABSTRACT:
An apparatus, program product and method perform static timing analysis on an integrated circuit design by concurrently modeling a plurality of timing delays associated with a connection between points in the design. The delays are conveyed in multiple clock signals of a single timing run of a static timing analysis operation. Multiple paths comprising logical user defined delay segments are assigned different delays. Only one signal may be permitted to propagate along each path.
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Non-Final Office Action for U.S. Appl. No. 12/126,053, mail date: Dec. 7, 2010, [16 pp].
Darsow Craig M.
Helvey Timothy D.
Chiang Jack
Dimyan Magid Y
International Business Machines - Corporation
Toler Law Group
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